Data lane returns to LP-11 after HS burst.
(v2.0 improvement) – clock lane enters LP-11 when idle, reducing power. mipi d phy 2.0 specification
MIPI D-PHY 2.0 compliance tests include: Data lane returns to LP-11 after HS burst
The primary advancement in D-PHY 2.0 is the increase in data rates, allowing it to handle higher-resolution imaging and display data. mipi d phy 2.0 specification
: In a standard four-lane configuration, a D-PHY 2.0 system can achieve an aggregate throughput of approximately 18 Gbps .